Patentanwaltskanzlei Kindermann in Baldham bei München - Spezialisiert auf Halbleitertechnik, Telekommunikation und Solartechnik

Semiconductor Technology

In the field of Semiconductor Technology our law firm encompasses everything from FOEL (Front End Of Line), e.g. semiconductor circuits realized in "strained silicon", to BEOL (Back End Of Line), e.g. "MIM caps" and the various "Damascene"-methods for manufacturing interconnect structures.

We have a long experience in all areas of integrated circuits, e.g. analogue semiconductor circuits, digital semiconductor circuits and so called "embedded circuits", thus enabling an effective support of our clients also with respect to complex technical issues. In this connection we would like to point out our sound knowledge, particularly, in Si-semiconductor technology. However, also special fields like GaAs-based semiconductor circuits are reliably handled by our firm.

With respect to semiconductor elements we have detailed technical knowledge both of standard elements, such as FETs (Field Effect Transistors), bipolar transistors, CMOS- and BiCMOS-circuits, DRAM memories, photodiodes, solar cells as well as of special technical fields, e.g. novel power semiconductor elements, the use of novel materials (e.g. high-k materials), respective manufacturing processes and the downsizing of semiconductor structures under sub-µ dimensions. Moreover, the so called "nano technology" represents a main focus of our activity.

Our respective technical knowledge is completed by the long experience in the field of wafer production, wafer handling, wafer processing as well as the related methods and systems of mask making and integrated circuit packaging. As a matter of course we have detailed knowledge with respect to the corresponding semiconductor equipment, such as ion implanter, diffusion furnace, wafer stepper, wafer transport means etc. Also with this technical aspect of semiconductor technology we may effectively present our detailed knowledge for the benefit of our clients, e.g. when elaborating and representing patent applications

Letzte Änderung am 21.02.17 um 03:30 Uhr.

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